Stavros Kalapothas, Georgios Flamis, Paris Kitsos, “Efficient Edge-AI Application Deployment for FPGAs”, Information 2022, 13(6), 279; https://doi.org/10.3390/info13060279 .
Ludwig Kapmel, Paris Kitsos, Dimitris Simos, “Locating Hardware Trojans Using Combinatorial Testing for Cryptographic Circuits”, IEEE Access, Vol. 10, pp: 18787 – 18806, 2022, DOI: 10.1109/ACCESS.2022.3151378.
Konstantinos G. Liakos, Georgios K. Georgakilas, Fotis C. Plessas, Paris Kitsos, “GAINESIS: Generative Artificial Intelligence NEtlists SynthesIS”, Electronics – Open Access Journal, Vol. 11, No. 2, 2022.
Georgios Flamis, Stavros Kalapothas, Paris Kitsos, “Best practices for the deployment of edge inference: The conclusions to start designing”, Electronics – Open Access Journal, Vol. 10, 2021.
C. Efstathiou and P. Kitsos, “Efficient majority logic magnitude comparator design”, Embedded Hardware Design: Microprocessors and Microsystems, Elsevier, Volume 82, April 2021.
Andreas Tsimpos, Andreas Christos Demartinos, Spyridon Vlassis, George Souliotis, “Multi-rate programmable equalizer for M-PHY serial interface”, IEEE Transactions on Emerging Topics in Computing, Manuscript Type: Special Issue, vol. 9, issue. 1, pp. 379-398, January 2021.
L. Pyrgas, P. Kitsos, “Compact Hardware Architectures of Enocoro-128v2 Stream Cipher for Constrained Embedded Devices”, Electronics – Open Access Journal, Vol. 9, Issue. 9, 1505-1519, 2020.
F. Pirpilidis, L. Pyrgas, P. Kitsos, “8-bit Serialised Architecture of SEED Block Cipher for Constrained Devices”, IET Circuits, Devices & Systems, 2020.
Apostolos Fournaris, Lampros Pyrgas, Paris Kitsos, “An Efficient Multi-parameter Approach for FPGA Hardware Trojan Detection”, Embedded Hardware Design: Microprocessors and Microsystems, Elsevier, Vol. 71, November 2019.
Spyridon Vlassis, George Souliotis, Fabian Khateb, Tomasz Kulej, “A 0.5V bulk-driven active voltage attenuator”, Circuits, Systems, and Signal Processing, 38, pp. 5883–5895, 2019.
Spyridon Vlassis, Fabian Khateb, George Souliotis, “An on-chip linear, squaring, cubic and exponential analog function generator”, IEEE Transactions on Circuits and Systems – I (CAS-I), January 2019, vol. 66, issue 1, pp. 94-104, doi: 10.1109/TCSI.2018.2841039.
Fotis Plessas, George Souliotis, Rodoula Makri, “A 76-84GHz CMOS 4x Subharmonic Mixer with Internal Phase Correction”, IEEE Transactions on Circuits and Systems – I (CAS-I), January 2018, vol. 65, issue 7, pp. 2083-2096.
George Souliotis, Fotis Plessas, Spyridon Vlassis, “A high accuracy voltage reference generator”, Microelectronics Journal, 75, 2018, pp. 61 – 67. https://authors.elsevier.com/a/1WhRe5~H7NSJG.
Andreas Tsimpos, Andreas Christos Demartinos, Spyridon Vlassis, George Souliotis, “A low-power frequency multiplier for multi-GHz applications”, IEEE Transactions on Emerging Topics in Computing, June 2018, vol. 6, issue 2, pp. 200 – 206. (doi:10.1109/TETC.2016.2582732).
F. Pirpilidis, K. G. Stefanidis, A. G. Voyiatzis, P. Kitsos, “Effect analysis of Ring Oscillator length and hardware Trojan size on an FPGA-based implementation of the AES algorithm”, Embedded Hardware Design: Microprocessors and Microsystems, Elsevier, Vol. 54, 2017.
Spyridon Vlassis, Tomasz Kulej, Fabian Khateb, George Souliotis, “0.5V bulk-driven ring amplifier based on master-slave technique”, Integrated Circuits & Signal Processing (ALOG), 90, pp. 189–197, 2017. DOI 10.1007/s10470-016-0858-2. http://rdcu.be/vFVd.
A. Demartinos, A. Tsimpos, S. Vlassis, G. Souliotis, “Jitter tolerance modeling and calibration for high-speed serial interfaces”, Integration, the VLSI Journal (Elsevier), vol. 57, pp. 101-107, 2017.
Andreas Demartinos, Andreas Tsimpos, Spiros Vlassis, George Souliotis. “Analogue feedback inverter based duty-cycle correction”, Analog Integrated Circuits and Signal Processing (ALOG/Springer), vol. 90, pp. 711–716, 2017. DOI 10.1007/s10470-016-0921-z.
Fabian Khateb, Spyridon Vlassis, Tomasz Kulej, George Souliotis, “Bulk-driven class AB fully-balanced differential difference amplifier”, Analog Integrated Circuits and Signal Processing, October 2017, vol. 93, Issue 1, pp. 179–187. http://rdcu.be/ugbj.
George Souliotis, Costas Laoudias, Fotis Plessas and Nikolaos Terzopoulos, “Phase interpolator with improved linearity”, Circuits, Systems and Signal Processing, 35(2), pp. 367-383, February 2016. (DOI: 10.1007/s00034-015-0082-9).
Andreas Tsimpos, Andreas Christos Demartinos, George Souliotis, Spiros Vlassis, “Multi-rate Phase Interpolator for High Speed Serial Interfaces”, Microelectronics Journal, vol. 54, pp. 40–47, August 2016. doi:10.1016/j.mejo.2016.05.008.
Andreas C. Demartinos, Andreas Tsimpos, Spyridon Vlassis, George Souliotis, Savvas Sgourenas. “A scalable Voltage Controlled Oscillator for Multi-rate High-Speed Interfaces”, Microelectronics Journal, vol. 55, pp. 134–142, September 2016. doi: 10.1016/j.mejo.2016.07.003.
Andreas Christos Demartinos, Andreas Tsimpos, Spyridon Vlassis, George Souliotis. “Delay Elements Suitable for CMOS Ring Oscillators”, Journal of Engineering Science and Technology Review, 9(4), pp. 98-101, 2016.
A. Fournaris, I. Zafeirakis, P. Kitsos, O Koufopavlou, “Comparing Elliptic Curve Point Multiplication Design Approaches for Cryptography”, Embedded Hardware Design: Microprocessors and Microsystems, Elsevier, 2015.
E. Cuevas-Farfan, M. Morales-Sandoval, A. Morales-Reyes, C. Feregrino-Uribe, I. Algredo-Badilio, P. Kitsos, R. Cumplido, “Karatsuba-Ofman Multiplier with Integrated Modular Reduction for (2^^m)”, Advances in Electrical and Computer Engineering, Volume 13, Number 2, 2013.
P. Kitsos, N. Sklavos, G. Provelengios, A. N. Skodras, “FPGA-based Performance Analysis of Stream Ciphers ZUC, Snow3g, Grain v1, Mickey v2, Trivium and E0”, Embedded Hardware Design: Microprocessors and Microsystems, Elsevier, Vol. 37, Issue 2, 2013.
Morales-Sandoval, C. Feregrino-Ubire, R. Cumplido, P. Kitsos, “Area/Performance trade-off analysis of an FPGA digit-serial GF(2^m) Montgomery Multiplier based on LFSR”, Computer and Electrical Engineering, Elsevier, Vol. 39, Issue 2, 2013.
L. Bisdounis, “Analytical modeling of overshooting effect in sub-100nm CMOS inverters, Journal of Circuits, Systems, and Computers”, World Scientific, vol. 20, no. 7, pp. 1303-1321, November 2011.
M. Morales-Sandoval, C. Feregrino-Uribe and P. Kitsos, “Bit-Serial and Digit-Serial GF(2^^m) Montgomery Multipliers using Linear Feedback Shift Registers”, IET Computers & Digital Techniques Journal, Vol. 5, Issue. 2, March 2011.
B. Geelen, V. Ferentinos, F. Catthoor, G. Lafruit, R. Lauwereins, D. Verkest, and T. Stouraitis, “Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements”, ACM Transactions on Embedded Computing Systems (TECS), 9(3): (2010).
B. Geelen, V. Ferentinos, F. Catthoor, S. Toulatos, G. Lafruit, T. Stouraitis, R. Lauwereins, and D. Verkest, “Exploiting varying resource requirements in wavelet-based applications in dynamic execution environments”, The Journal of Signal Processing Systems, 2009, Volume 56, Numbers 2-3.
B. Geelen, V. Ferentinos, F. Catthoor, G. Lafruit, D. Verkest, R. Lauwereins, and T. Stouraitis, “Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts”, ACM Transaction on Design Automation of Electronic Systems (TODAES), 15(1): (2009).
P. Kitsos, N. Sklavos, and O. Koufopavlou, “UMTS Security: System Architecture and Hardware Implementation”, Wireless Communications and Mobile Computing Journal, Volume 7, Issue 4, May 2007.
S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas, “Instruction-level energy modeling for pipelined processors, Journal of Embedded Computing”, IOS Press, vol. 1, no. 3 (special issue on low-power embedded systems), pp. 317-324, March 2006.
N. Sklavos, P. Kitsos, K. Papadopoulos and O. Koufopavlou, “Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security (WTLS)”, Journal of Supercomputing, Kluwer Academic Publishers, Volume 36, No. 1, pp: 33-50, 2006.
P. Kitsos, M. D. Galanis, and O. Koufopavlou, “An FPGA Implementation of the GPRS Encryption Algorithm 3 (GEA3)”, Journal of Circuits, Systems, and Computers (JCSC), World Scientific Publishing Company, Vol. 14, No. 2, pp: 217-231, 2005.
V. Ferentinos, B. Geelen, G. Lafruit, M. Milia, J. Bormans, F. Catthoor, and T. Stouraitis, “Optimized memory requirements for wavelet-based scalable multimedia codecs”, Journal of Embedded Computing (JEC), vol. 1, no. 3, pages 363–380, 2005.
L. Bisdounis, C. Dre, S. Blionas, D. Metafas, A. Tatsaki, F. Ieromnimon, E. Macii, Ph. Rouzet, R. Zafalon, L. Benini, “Low-power system-on-chip architecture for wireless LANs”, IEE Computers and Digital Techniques, vol. 151, no. 1, pp. 2-15, January 2004.
G. Lafruit, E. Delfosse, R. Osorio, W. van Raemdonck, V. Ferentinos, J. Bormans, “View-dependent, scalable Texture Streaming in 3D QoS with MPEG-4 Visual Texture Coding”, IEEE Tr. Circuits and Systems for Video technology, Vol. 14: (7) 1021-1031; 2004.
C. Drosos, L. Bisdounis, D. Metafas, S. Blionas, A. Tatsaki, G. Papadopoulos, “Hardware-software design and validation framework for wireless LAN modems”, IET Computers and Digital Techniques, vol. 151, no. 3, pp. 173-182, May 2004.
P. Kitsos, N. Sklavos, M. D. Galanis, and O. Koufopavlou, “64-bit Block Ciphers: Hardware Implementation and Comparison Analysis”, Computers and Electrical Engineering, Elsevier Science, Vol. 30, Issue: 8, pp. 593-604, November 2004.
P. Kitsos and O. Koufopavlou, “Efficient Architecture and Hardware Implementation of the Whirlpool Hash Function”, IEEE Transactions on Consumer Electronics, Vol. 50, Issue 1, February 2004, pp. 208-213.
P. Kitsos, G. Theodoridis, and O. Koufopavlou, “An Efficient Reconfigurable Multiplier Architecture for Galois field GF(2^^m)”, Elsevier Microelectronics Journal, Vol. 34, Issue 10, October 2003, pp. 975-980.
P. Kitsos, N. Sklavos, K. Papadomanolakis and O. Koufopavlou, “Hardware Implementation of the Bluetooth Security”, IEEE Pervasive Computing, Mobile and Ubiquitous Systems, Vol. 2, No. 1, Jan.-Mar. 2003, pp. 21-29.